http://www.thss.tsinghua.edu.cn/faculty_xiangd_cn.asp
向东 教授
清华大学 教授 博士生导师
电子邮件： dxiang@tsinghua.edu.cn
办公电话： 86-10-62795434
主要经历：
于1987及1990年毕业于重庆大学获计算机科学学士学位及硕士学位。
1993年于中国科学院计算技术研究所获得计算机工程博士学位。
1994-1995为加拿大，Concordia大学电子工程系博士后，
1995-1996为美国Illinois大学，Urbana Champaign, 电子工程系(Coordinated Science Lab.)博士后。
1996.10 -2003.3为清华大学，微电子学研究所副教授。
2003.3-2004.12为清华大学软件学院副教授。
2003.4-2003.9为日本奈良先端科大JSPS研究员。
现为清华大学软件学院教授， 博士生导师。
研究领域：
数字系统测试与设计：可测试性设计，可测试性分析，低成本测试，自测试，测试码产生；容错计算，并行/分布式计算，计算机网络通讯
主要奖励：
2003: JSPS fellowship;
2004: 国家杰出青年基金；
2004：IEEE Senior Member。
获得专利
1.向东，孙家广，降低非扫描可测试性设计管脚开销的方法，国家发明专利，专利号：ZL 02 1 46776.5, 2004.12。
2．D. Xiang, J. Sun, M. Chen, and S. Gu, Cost-Effective Scan Architecture and a Test Application Scheme, US Patent US 6,959,426 B2, Oct. 25, 2005.
3．向东，孙家广,李开伟， A New Test Point Architecture for High-Quality Testability Design, US Patent,US 7,051,302 B2 , May 23, 2006.
4．向东，孙家广,李开伟, 基于扫描森林的扫描测试方法, 国家发明专利，ZL02159931.9， (2006.8)。
另有三项国家发明专利获批。申请了10余国家发明专利，及三项美国国际发明专利。
目前开设课程
1．分布式系统 （着重介绍互连网络高性能，无死锁及容错通讯，教材,J. Duato, L. Ni, S. Yalamanchili, Interconnection Networks: An Engineering Approach, IEEE Press, 1997, 及2002版本， 每年秋季）。
主要在研项目：
1．采用新的扫描链构造技术提高BIST的测试效率，国家自然科学基金（负责人，2004.1-2006.12）。
2．数字系统可测试性设计理论研究， 国家杰出青年基金（负责人，2005.1- 2008.12）。
3．基于路由技术多计算机网络的容错组播及广播, 国家自然科学基金（负责人，2006.1-2008.12）。
4．大规模自组织无线网络低功耗，高可靠性路由技术, 国家863 探索导向类项目 (负责人, 2007.1-2009.12).
专业任职：
期刊杂志：
IEEE Senior Member, IEEE Trans. Computers, IEEE Trans. Computer-Aided Design, IEEE Trans. Parallel and Distributed Systems, J. of Parallel and Distributed Computing,IEEE Trans. VLSI Systems, IEEE Trans. Reliability, IEEE Int. Test Conference, ACM/IEEE Design Automation Conference, Int. Conf. on Parallel Processing, IEE Proc. Part E, Inform. Sci.等杂志及会议评审人；《中国科学》等审稿人.
会议：
[1] 12th , 14th , 16th, 17th IEEE Asian Test Symposium(2008) 程序委员会委员；
[2] 11th , 12th , 13th, 14th IEEE Pacific Rim Dependable Computing Conf.(2008), 程序委员会委员；
[3] 28th IEEE Int. Conference on Distributed Computing Systems，2008, 程序委员会委员；
[4] 19th IEEE Int. Conference on Computer Communications and Networks, 2008, 程序委员会委员；
[5] 8th Int. Conf. on Young Computer Scientists, 2008, 程序委员会委员；
[6] Int. Conf. on Algorithms and Architectures for Parallel Processing, 2008, 程序委员会委员；
[7] 10th IEEE Int. Conf. on High-Performance Computing and Communication, 2008, 程序委员会委员。
[8] 19th IEEE Asian Test Symp.(2010), 15th IEEE Pacific Rim Dependable Computing Symposium(2009), 程序委员会主席。
[9] Int. Conf. on Reliability and Safety Engineering2005 and INCRESE2006， 及INCRESE2007 指导委员会委员；
[10] IEEE Int. Workshop on RTL and High- Level Testing指导委员会委员;
A keynote address at INCRESE2005(India)。
有代表性的论著：
非扫描可测试性设计：
[1] D. Xiang, Y. Xu, and H. Fujiwara, “Non-scan design for testability for synchronous sequential circuits based on conflict resolution,” IEEE Trans. on Computers, vol. 52, no. 8, pp. 1063-1075, 2003.
[2] D. Xiang and H. Fujiwara, “Handling the pin overhead problem for high quality and at-speed test,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 9, pp. 1105-1113, 2002.
[3] D. Xiang and Y. Xu, “Cost-effective non-scan design for testability for synchronous sequential circuits,” Proc. of 19th? IEEE Int. Conference on Computer Design, pp.154-159 , Austin, USA, Sept, 2001.
[4] D. Xiang and Y. Xu, “Partial reset for synchronous sequential circuits using almost independent reset signals,” Proc. of 19th? IEEE VLSI Test Symposium, pp.82-87, Los Angels, April, 2001.
[5] D. Xiang, S. Gu, and H. Fujiwara, “Non-scan design for testability based on fault-oriented conflict analysis,”? Proc. of? 11th? IEEE Asian Test Symposium, Guam, USA, Nov., 2002.
[6] D. Xiang, S. Gu, and H. Fujiwara, “Non-scan design for testability for? mixed RTL circuits with both data paths and controller via conflict analysis,” Proc. of 12th IEEE Asian Test Symposium, pp. 300-303, 2003.
[7] D. Xiang, S. Gu, and H. Fujiwara, “Non-scan design for testability for synchronous sequential circuits based on fault-oriented conflict analysis,” IEICE Trans. on Information and Systems, vol.E86-D, pp. 2407-2417, Nov., 2003.
低成本扫描测试：
[8] D. Xiang, S. Gu, J. Sun, and D. Wu, “Cost-effective scan design with non-scan test application cost and test power,” in Proc. of ACM/IEEE Design Automation Conference, pp. 744-747, June, Anaheim, 2003.
[9] D. Xiang, K. Li, and H. Fujiwara, “Design for scan testing with low test application cost and low test data volume by reconstructing scan flip-flops,”? in Proc. of 14th IEEE Asian Test Symposium, pp. 318-321, Dec., 2005.
[10] D. Xiang, K. Li, and H. Fujiwara, “Localizing test power consumption for scan testing,” in Proc. of 6th IEEE Int. Workshop on RTL and High Level Testing, pp. 18-23, 2005.
[11] D. Xiang and K. Li, “Low Power Scan testing using a two-stage scan architecture,”? Chinese Journal of Computers, pp. 786-791, no. 5, 2006 (in Chinese).
[12] K. Li and D. Xiang, “Scan testing with low power, test application time and reduced test data volume,” Journal of Tsinghua University, pp. 98-101, no. 1, 2006(in Chinese).
[13] D. Xiang, K. Li, J. Sun, and H. Fujiwara, “Reconfigured scan forest for test application cost, test data volume and test power reduction,” IEEE Trans. on Computers, vol. 56, no. 4, pp. 557-562, April 2007.
[14] D. Xiang, K. Li, H. Fujiwara, K. Thulasiraman, and J. Sun, “Constraining transition propagation for low power scan testing using a two-stage scan architecture,” ?IEEE Trans. Circuits and Systems-II, vol. 54, no. 5, pp. 450-454, May 2007.
[15] Q. Xu, D. Hu, and D. Xiang, “Pattern-directed circuit partitioning for test power reduction,” accepted to appear in Proc. of IEEE Int. Test Conference, Santa Clara, Oct. 2007.
部分扫描设计
[16] D. Xiang and J.H.Patel, “Partial scan design based on valid state information and functional information,” IEEE Trans. on Computers, vol.53, no.3, pp.276-287, 2004.
[17] D. Xiang and Y. Xu, “A multiple phase partial scan design method,” Proc. of 10th??IEEE Asian Test Symposium, Kyoto, pp.17-22, Nov., 2001.
[18]D. Xiang and J. Patel, “A global algorithm for the partial scan design problem using circuit state information,” in ?Proc. of IEEE Int. Test Conference, pp. 548-557, Nov., 1996.
自测试
[19] D. Xiang, M. J. Chen, J. G. Sun, and H. Fujiwara, “Improving the effectiveness of scan-based BIST using scan chain partitioning,” IEEE Trans. on Computer-Aided Design, vol. 24, no. 6, pp.916-927, 2005.
[20] D. Xiang, M. J. Chen, J. Sun, and H. Fujiwara, “Improving test quality of scan-based BIST by scan chain partitioning,” Proc. of 12th IEEE Asian Test Symposium, pp.12-17, 2003.
[21] D. Xiang, M. Chen, K. Li, and D. Wu, “Scan-based BIST using an improved scan forest architecture,” ?in Proc. of ?13th IEEE Asian Test Symposium, pp. 88-93, Nov., 2004.
[22] D. Xiang, D. Z. Wei, and S. S. Chen, “A global test point placement algorithm for combinational circuits,” Proc. of 5th? IEEE Int. Conf. on VLSI Design, pp. 227-232, 1992.
[23] D. Xiang and D. Z. Wei, “Global: A design for random testability algorithm,” J. of Computer Science and Technology, vol. 9, no. 2, pp. 182-192, 1994.
[24] D. Xiang, D. Z. Wei, and S. S. Chen, “Probabilistic models for estimation of random and pseudorandom test length,” J. of Computer Science and Technology, vol. 7, no.2, pp. 164-174, 1992.
[25] D.Xiang,“Knowledge-based design for testability,”ActaElectronica Sinica, vol. 19, no. 3,pp. 106-109, 1991(in Chinese).
[26] D. Xiang, M. Chen, and H. Fujiwara, “Using weighted scan enable signals to improve test effectiveness of scan-based BIST,”? in? Proc. 14th IEEE Asian Test Symposium, pp. 126-131, Dec., 2005.
[27] D. Xiang, Y. Zhao, K. Chakrabarty, J. Sun, and H. Fujiwara, “Compressing test data for deterministic BIST using a reconfigurable scan architecture,” in ?Proc. of 15th IEEE Asian Test Symposium, Japan, pp.299-304, Nov., 2006.
[28] D. Xiang, M. Chen, and J. Sun, “Using weighted scan enable signals to improve the test effectiveness of scan-based BIST,” Science in China, vol. 36, no. 8, pp. 902-911, 2006 (in Chinese).
[29] D. Xiang, M. Chen, and J. Sun, “Improving test effectiveness of scan-based BIST by using weighted scan enable signals,” accepted to appear in Science in China (English version), 2006.
[30] D. Xiang, M. J. Chen, and H. Fujiwara,“Using weighted scan enable signals to improve test effectiveness of scan-based BIST,”accepted to appear in IEEE Trans. On Computers, 2007.
[31] D. Xiang, Y. Zhao, K. Chakrabarty, and H. Fujiwara, “A reconfigurable scan architecture with weighted scan enable signals for deterministic BIST,” accepted to appear in IEEE Trans. on Coputer-Aided Design, 2008.
可测试性分析
[32] D. Xiang, Y. Xu, and H. Fujiwara, “Non-scan design for testability for synchronous sequential circuits based on conflict analysis,” Proc. of IEEE Int. Test Conference, Atlantic City, pp. 420-429, Oct., 2000.
[33] D. Xiang, S. Venkataraman, K. Fuchs, and J. Patel, “Partial scan design based on circuit state information,” Proc. 33th?? of ACM/IEEE Design Automation Conference, pp. 807-8l2, Las Vegas, l996.
[34] D. Xiang, “SCTM: A conflict oriented testability measure,” Chinese Journal of Computers, vol. 16,? no. 4,? pp. 273-280, 1993 (in Chinese).
[35] D. Xiang and D. Z. Wei,? “On functional circuit testability analysis,”? Chinese Journal of Computers,? vol. 16, no. 1, pp. 35-44, 1993 (in Chinese).
延迟测试
[36] D. Xiang, K. Li, H. Fujiwara, and J. Sun, “Generating compact robust and non-robust tests for complete coverage of path delay faults based on stuck-at tests,” in Proc. of 24th IEEE Int. Conference on Computer Design, pp. 446-451, 2006.
[37] D. Xiang, Y. Zhao, K. Li, and H. Fujiwara, “Fast and effective fault simulation for path delay faults based on selected testable paths,” accepted to appear in Proc. of IEEE Int. Test Conference, Santa Clara, Oct. 2007.
[38] D. Xiang, K. Chakrabarty, D. Hu, and H. Fujiwara, “Scan testing for complete coverage of path delay faults with reduced test data volume, test application time and hardware,” accepted to appear in Proc. of 16th IEEE Asian Test Symposium, Oct. 2007.
容错计算
[39] D. Xiang, “Fault-tolerant routing in hypercube multicomputers using local safety information,” IEEE Trans. on Parallel and Distributed Systems, vol. 12, no. 9, pp. 942-951, 2001.
[40] D. Xiang and A. Chen, “Reliable broadcasting in wormhole-routed? hypercube -connected networks using local safety information,”IEEE Trans. on Reliability, pp. 245-256, vol. 52, no. 2, June, 2003.
[41] D. Xiang, A. Chen, and J. Wu, “Fault-tolerant broadcasting for hypercubes? based on local safety information,” Proc. of 9th? IEEE Int. Conf. on Parallel and Distributed Systems,? pp. 31-36, Taiwan, Dec.,? 2002.
[42] D. Xiang and J. Wu, “Reliable multicasting for hypercube multicomputers using local safety information,” Proc. of? 13th? Int. Conf. on Parallel and Distributed Computing Systems, Las Vegas, Aug., pp. 529-534, 2000.
[43] D.Xiang, A.Chen, and J. Wu, “Local-safety-information-based broadcasting in hypercube multicomputers with node and link faults,” Int. Journal of Interconnection Networks, vol. 2,no. 3, World Scientific Publishers, pp. 365-378, 2001(invited? paper).
[44] D. Xiang and J. Wu, “Reliable unicasting in faulty hypercubes using local safety information,” Proc. of 4th? IEEE Int. Conf. on? Algorithms and Architectures for Parallel Processing,? Hong Kong,? Dec., 2000.
[45] D. Xiang, “Partial path set-up for fault-tolerant? routing in hypercube multicomputers,” Future Generation Computer Systems, vol. 22, pp. 812-819, Elsevier Scientific Press, Aug., 2006.
[46] D. Xiang, A. Chen, and J. Wu,“Local-safety-information-based ?fault-tolerant broadcasting in hypercubes,” J. of Inform. Sci. and Eng., vol. 19, no. 3, pp.467-478, June, 2003.
[47] D. Xiang and A. Chen, “Fault-tolerant routing in hypercubes based on partial path set-up, ” in Proc.of 2003 IEEE Int. Workshop on PMEO-PDS03 (with IPDPS03), IEEE Computer Society Press.
[48] D. Xiang,? A. Chen, and J. Sun,? “Fault-tolerant routing in 3D meshes/tori based on locally formed fault blocks,”? Chinese Journal of Computers,? vol. 27,? no. 5,? pp. 611-618, 2004 (in Chinese).
[49] D. Xiang, A. Chen, and J. G. Sun, “Fault-tolerant multicasting in hypercube multicomputers using local safety information,” Journal of Parallel and Distributed Computing, vol. 66, no. 2, ?pp. 248-256, 2006.
并行/分布式计算
[50] D. Xiang, Y. Zhang, Y. Pan, and J. Wu, “Deadlock-free adaptive routing in meshes based on cost-effective deadlock avoidance schemes,”accepted to appear in 36th IEEE Int. Conference on Parallel Processing, Sept. 2007.
[51] D. Xiang, A. Chen, and J. Sun, “Fault-tolerant routing and multicasting for hypercube multicomputers based on partial path set-up,”? Parallel Computing, Elsevier Science Press, vol.31, no. 1,? pp. 389-411, 2005.
[52] D. Xiang, J. Sun, J. Wu, and K. Thulasiraman, “Fault-tolerant routing in meshes /tori using planarly constructed fault blocks,”? in Proc. of 34th IEEE Int Conference on Parallel Processing, pp. 577-584, Oslo, Norway, 2005.
[53] D. Xiang and A. Chen, “Fault-tolerant routing in 2D meshes/tori using limited -global-safety information,” Proc. of 31th? IEEE Int. Conf. on Parallel Processing, pp. 231-238,? Vancouver, Aug.,? 2002.
[54] 向东，张跃鲤，mesh网高效无死锁路由算法，《计算机学报》，vol. 30, no. 11, pp. 1954-1963, 2007.
[55] Z. Li , Y. Zhao, Y. Cui, and D. Xiang, “A density adaptive routing protocol for large-scale Ad hoc networks,” accepted to appear in Proc. of IEEE Wireless Communications and Networking Conference, 2008.
[56] D. Xiang, Y. Pan, Q. Wang, and Z. Chen, “Deadlock-free fully adaptive routing in 2-dimensional tori based on a new virtual network partitioning scheme,” accepted to appear in Proc. of 28th IEEE Int. Conference on Distributed Computing Systems, 2008.
向东 教授
清华大学 教授 博士生导师
电子邮件： dxiang@tsinghua.edu.cn
办公电话： 86-10-62795434
主要经历：
于1987及1990年毕业于重庆大学获计算机科学学士学位及硕士学位。
1993年于中国科学院计算技术研究所获得计算机工程博士学位。
1994-1995为加拿大，Concordia大学电子工程系博士后，
1995-1996为美国Illinois大学，Urbana Champaign, 电子工程系(Coordinated Science Lab.)博士后。
1996.10 -2003.3为清华大学，微电子学研究所副教授。
2003.3-2004.12为清华大学软件学院副教授。
2003.4-2003.9为日本奈良先端科大JSPS研究员。
现为清华大学软件学院教授， 博士生导师。
研究领域：
数字系统测试与设计：可测试性设计，可测试性分析，低成本测试，自测试，测试码产生；容错计算，并行/分布式计算，计算机网络通讯
主要奖励：
2003: JSPS fellowship;
2004: 国家杰出青年基金；
2004：IEEE Senior Member。
获得专利
1.向东，孙家广，降低非扫描可测试性设计管脚开销的方法，国家发明专利，专利号：ZL 02 1 46776.5, 2004.12。
2．D. Xiang, J. Sun, M. Chen, and S. Gu, Cost-Effective Scan Architecture and a Test Application Scheme, US Patent US 6,959,426 B2, Oct. 25, 2005.
3．向东，孙家广,李开伟， A New Test Point Architecture for High-Quality Testability Design, US Patent,US 7,051,302 B2 , May 23, 2006.
4．向东，孙家广,李开伟, 基于扫描森林的扫描测试方法, 国家发明专利，ZL02159931.9， (2006.8)。
另有三项国家发明专利获批。申请了10余国家发明专利，及三项美国国际发明专利。
目前开设课程
1．分布式系统 （着重介绍互连网络高性能，无死锁及容错通讯，教材,J. Duato, L. Ni, S. Yalamanchili, Interconnection Networks: An Engineering Approach, IEEE Press, 1997, 及2002版本， 每年秋季）。
主要在研项目：
1．采用新的扫描链构造技术提高BIST的测试效率，国家自然科学基金（负责人，2004.1-2006.12）。
2．数字系统可测试性设计理论研究， 国家杰出青年基金（负责人，2005.1- 2008.12）。
3．基于路由技术多计算机网络的容错组播及广播, 国家自然科学基金（负责人，2006.1-2008.12）。
4．大规模自组织无线网络低功耗，高可靠性路由技术, 国家863 探索导向类项目 (负责人, 2007.1-2009.12).
专业任职：
期刊杂志：
IEEE Senior Member, IEEE Trans. Computers, IEEE Trans. Computer-Aided Design, IEEE Trans. Parallel and Distributed Systems, J. of Parallel and Distributed Computing,IEEE Trans. VLSI Systems, IEEE Trans. Reliability, IEEE Int. Test Conference, ACM/IEEE Design Automation Conference, Int. Conf. on Parallel Processing, IEE Proc. Part E, Inform. Sci.等杂志及会议评审人；《中国科学》等审稿人.
会议：
[1] 12th , 14th , 16th, 17th IEEE Asian Test Symposium(2008) 程序委员会委员；
[2] 11th , 12th , 13th, 14th IEEE Pacific Rim Dependable Computing Conf.(2008), 程序委员会委员；
[3] 28th IEEE Int. Conference on Distributed Computing Systems，2008, 程序委员会委员；
[4] 19th IEEE Int. Conference on Computer Communications and Networks, 2008, 程序委员会委员；
[5] 8th Int. Conf. on Young Computer Scientists, 2008, 程序委员会委员；
[6] Int. Conf. on Algorithms and Architectures for Parallel Processing, 2008, 程序委员会委员；
[7] 10th IEEE Int. Conf. on High-Performance Computing and Communication, 2008, 程序委员会委员。
[8] 19th IEEE Asian Test Symp.(2010), 15th IEEE Pacific Rim Dependable Computing Symposium(2009), 程序委员会主席。
[9] Int. Conf. on Reliability and Safety Engineering2005 and INCRESE2006， 及INCRESE2007 指导委员会委员；
[10] IEEE Int. Workshop on RTL and High- Level Testing指导委员会委员;
A keynote address at INCRESE2005(India)。
有代表性的论著：
非扫描可测试性设计：
[1] D. Xiang, Y. Xu, and H. Fujiwara, “Non-scan design for testability for synchronous sequential circuits based on conflict resolution,” IEEE Trans. on Computers, vol. 52, no. 8, pp. 1063-1075, 2003.
[2] D. Xiang and H. Fujiwara, “Handling the pin overhead problem for high quality and at-speed test,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 9, pp. 1105-1113, 2002.
[3] D. Xiang and Y. Xu, “Cost-effective non-scan design for testability for synchronous sequential circuits,” Proc. of 19th? IEEE Int. Conference on Computer Design, pp.154-159 , Austin, USA, Sept, 2001.
[4] D. Xiang and Y. Xu, “Partial reset for synchronous sequential circuits using almost independent reset signals,” Proc. of 19th? IEEE VLSI Test Symposium, pp.82-87, Los Angels, April, 2001.
[5] D. Xiang, S. Gu, and H. Fujiwara, “Non-scan design for testability based on fault-oriented conflict analysis,”? Proc. of? 11th? IEEE Asian Test Symposium, Guam, USA, Nov., 2002.
[6] D. Xiang, S. Gu, and H. Fujiwara, “Non-scan design for testability for? mixed RTL circuits with both data paths and controller via conflict analysis,” Proc. of 12th IEEE Asian Test Symposium, pp. 300-303, 2003.
[7] D. Xiang, S. Gu, and H. Fujiwara, “Non-scan design for testability for synchronous sequential circuits based on fault-oriented conflict analysis,” IEICE Trans. on Information and Systems, vol.E86-D, pp. 2407-2417, Nov., 2003.
低成本扫描测试：
[8] D. Xiang, S. Gu, J. Sun, and D. Wu, “Cost-effective scan design with non-scan test application cost and test power,” in Proc. of ACM/IEEE Design Automation Conference, pp. 744-747, June, Anaheim, 2003.
[9] D. Xiang, K. Li, and H. Fujiwara, “Design for scan testing with low test application cost and low test data volume by reconstructing scan flip-flops,”? in Proc. of 14th IEEE Asian Test Symposium, pp. 318-321, Dec., 2005.
[10] D. Xiang, K. Li, and H. Fujiwara, “Localizing test power consumption for scan testing,” in Proc. of 6th IEEE Int. Workshop on RTL and High Level Testing, pp. 18-23, 2005.
[11] D. Xiang and K. Li, “Low Power Scan testing using a two-stage scan architecture,”? Chinese Journal of Computers, pp. 786-791, no. 5, 2006 (in Chinese).
[12] K. Li and D. Xiang, “Scan testing with low power, test application time and reduced test data volume,” Journal of Tsinghua University, pp. 98-101, no. 1, 2006(in Chinese).
[13] D. Xiang, K. Li, J. Sun, and H. Fujiwara, “Reconfigured scan forest for test application cost, test data volume and test power reduction,” IEEE Trans. on Computers, vol. 56, no. 4, pp. 557-562, April 2007.
[14] D. Xiang, K. Li, H. Fujiwara, K. Thulasiraman, and J. Sun, “Constraining transition propagation for low power scan testing using a two-stage scan architecture,” ?IEEE Trans. Circuits and Systems-II, vol. 54, no. 5, pp. 450-454, May 2007.
[15] Q. Xu, D. Hu, and D. Xiang, “Pattern-directed circuit partitioning for test power reduction,” accepted to appear in Proc. of IEEE Int. Test Conference, Santa Clara, Oct. 2007.
部分扫描设计
[16] D. Xiang and J.H.Patel, “Partial scan design based on valid state information and functional information,” IEEE Trans. on Computers, vol.53, no.3, pp.276-287, 2004.
[17] D. Xiang and Y. Xu, “A multiple phase partial scan design method,” Proc. of 10th??IEEE Asian Test Symposium, Kyoto, pp.17-22, Nov., 2001.
[18]D. Xiang and J. Patel, “A global algorithm for the partial scan design problem using circuit state information,” in ?Proc. of IEEE Int. Test Conference, pp. 548-557, Nov., 1996.
自测试
[19] D. Xiang, M. J. Chen, J. G. Sun, and H. Fujiwara, “Improving the effectiveness of scan-based BIST using scan chain partitioning,” IEEE Trans. on Computer-Aided Design, vol. 24, no. 6, pp.916-927, 2005.
[20] D. Xiang, M. J. Chen, J. Sun, and H. Fujiwara, “Improving test quality of scan-based BIST by scan chain partitioning,” Proc. of 12th IEEE Asian Test Symposium, pp.12-17, 2003.
[21] D. Xiang, M. Chen, K. Li, and D. Wu, “Scan-based BIST using an improved scan forest architecture,” ?in Proc. of ?13th IEEE Asian Test Symposium, pp. 88-93, Nov., 2004.
[22] D. Xiang, D. Z. Wei, and S. S. Chen, “A global test point placement algorithm for combinational circuits,” Proc. of 5th? IEEE Int. Conf. on VLSI Design, pp. 227-232, 1992.
[23] D. Xiang and D. Z. Wei, “Global: A design for random testability algorithm,” J. of Computer Science and Technology, vol. 9, no. 2, pp. 182-192, 1994.
[24] D. Xiang, D. Z. Wei, and S. S. Chen, “Probabilistic models for estimation of random and pseudorandom test length,” J. of Computer Science and Technology, vol. 7, no.2, pp. 164-174, 1992.
[25] D.Xiang,“Knowledge-based design for testability,”ActaElectronica Sinica, vol. 19, no. 3,pp. 106-109, 1991(in Chinese).
[26] D. Xiang, M. Chen, and H. Fujiwara, “Using weighted scan enable signals to improve test effectiveness of scan-based BIST,”? in? Proc. 14th IEEE Asian Test Symposium, pp. 126-131, Dec., 2005.
[27] D. Xiang, Y. Zhao, K. Chakrabarty, J. Sun, and H. Fujiwara, “Compressing test data for deterministic BIST using a reconfigurable scan architecture,” in ?Proc. of 15th IEEE Asian Test Symposium, Japan, pp.299-304, Nov., 2006.
[28] D. Xiang, M. Chen, and J. Sun, “Using weighted scan enable signals to improve the test effectiveness of scan-based BIST,” Science in China, vol. 36, no. 8, pp. 902-911, 2006 (in Chinese).
[29] D. Xiang, M. Chen, and J. Sun, “Improving test effectiveness of scan-based BIST by using weighted scan enable signals,” accepted to appear in Science in China (English version), 2006.
[30] D. Xiang, M. J. Chen, and H. Fujiwara,“Using weighted scan enable signals to improve test effectiveness of scan-based BIST,”accepted to appear in IEEE Trans. On Computers, 2007.
[31] D. Xiang, Y. Zhao, K. Chakrabarty, and H. Fujiwara, “A reconfigurable scan architecture with weighted scan enable signals for deterministic BIST,” accepted to appear in IEEE Trans. on Coputer-Aided Design, 2008.
可测试性分析
[32] D. Xiang, Y. Xu, and H. Fujiwara, “Non-scan design for testability for synchronous sequential circuits based on conflict analysis,” Proc. of IEEE Int. Test Conference, Atlantic City, pp. 420-429, Oct., 2000.
[33] D. Xiang, S. Venkataraman, K. Fuchs, and J. Patel, “Partial scan design based on circuit state information,” Proc. 33th?? of ACM/IEEE Design Automation Conference, pp. 807-8l2, Las Vegas, l996.
[34] D. Xiang, “SCTM: A conflict oriented testability measure,” Chinese Journal of Computers, vol. 16,? no. 4,? pp. 273-280, 1993 (in Chinese).
[35] D. Xiang and D. Z. Wei,? “On functional circuit testability analysis,”? Chinese Journal of Computers,? vol. 16, no. 1, pp. 35-44, 1993 (in Chinese).
延迟测试
[36] D. Xiang, K. Li, H. Fujiwara, and J. Sun, “Generating compact robust and non-robust tests for complete coverage of path delay faults based on stuck-at tests,” in Proc. of 24th IEEE Int. Conference on Computer Design, pp. 446-451, 2006.
[37] D. Xiang, Y. Zhao, K. Li, and H. Fujiwara, “Fast and effective fault simulation for path delay faults based on selected testable paths,” accepted to appear in Proc. of IEEE Int. Test Conference, Santa Clara, Oct. 2007.
[38] D. Xiang, K. Chakrabarty, D. Hu, and H. Fujiwara, “Scan testing for complete coverage of path delay faults with reduced test data volume, test application time and hardware,” accepted to appear in Proc. of 16th IEEE Asian Test Symposium, Oct. 2007.
容错计算
[39] D. Xiang, “Fault-tolerant routing in hypercube multicomputers using local safety information,” IEEE Trans. on Parallel and Distributed Systems, vol. 12, no. 9, pp. 942-951, 2001.
[40] D. Xiang and A. Chen, “Reliable broadcasting in wormhole-routed? hypercube -connected networks using local safety information,”IEEE Trans. on Reliability, pp. 245-256, vol. 52, no. 2, June, 2003.
[41] D. Xiang, A. Chen, and J. Wu, “Fault-tolerant broadcasting for hypercubes? based on local safety information,” Proc. of 9th? IEEE Int. Conf. on Parallel and Distributed Systems,? pp. 31-36, Taiwan, Dec.,? 2002.
[42] D. Xiang and J. Wu, “Reliable multicasting for hypercube multicomputers using local safety information,” Proc. of? 13th? Int. Conf. on Parallel and Distributed Computing Systems, Las Vegas, Aug., pp. 529-534, 2000.
[43] D.Xiang, A.Chen, and J. Wu, “Local-safety-information-based broadcasting in hypercube multicomputers with node and link faults,” Int. Journal of Interconnection Networks, vol. 2,no. 3, World Scientific Publishers, pp. 365-378, 2001(invited? paper).
[44] D. Xiang and J. Wu, “Reliable unicasting in faulty hypercubes using local safety information,” Proc. of 4th? IEEE Int. Conf. on? Algorithms and Architectures for Parallel Processing,? Hong Kong,? Dec., 2000.
[45] D. Xiang, “Partial path set-up for fault-tolerant? routing in hypercube multicomputers,” Future Generation Computer Systems, vol. 22, pp. 812-819, Elsevier Scientific Press, Aug., 2006.
[46] D. Xiang, A. Chen, and J. Wu,“Local-safety-information-based ?fault-tolerant broadcasting in hypercubes,” J. of Inform. Sci. and Eng., vol. 19, no. 3, pp.467-478, June, 2003.
[47] D. Xiang and A. Chen, “Fault-tolerant routing in hypercubes based on partial path set-up, ” in Proc.of 2003 IEEE Int. Workshop on PMEO-PDS03 (with IPDPS03), IEEE Computer Society Press.
[48] D. Xiang,? A. Chen, and J. Sun,? “Fault-tolerant routing in 3D meshes/tori based on locally formed fault blocks,”? Chinese Journal of Computers,? vol. 27,? no. 5,? pp. 611-618, 2004 (in Chinese).
[49] D. Xiang, A. Chen, and J. G. Sun, “Fault-tolerant multicasting in hypercube multicomputers using local safety information,” Journal of Parallel and Distributed Computing, vol. 66, no. 2, ?pp. 248-256, 2006.
并行/分布式计算
[50] D. Xiang, Y. Zhang, Y. Pan, and J. Wu, “Deadlock-free adaptive routing in meshes based on cost-effective deadlock avoidance schemes,”accepted to appear in 36th IEEE Int. Conference on Parallel Processing, Sept. 2007.
[51] D. Xiang, A. Chen, and J. Sun, “Fault-tolerant routing and multicasting for hypercube multicomputers based on partial path set-up,”? Parallel Computing, Elsevier Science Press, vol.31, no. 1,? pp. 389-411, 2005.
[52] D. Xiang, J. Sun, J. Wu, and K. Thulasiraman, “Fault-tolerant routing in meshes /tori using planarly constructed fault blocks,”? in Proc. of 34th IEEE Int Conference on Parallel Processing, pp. 577-584, Oslo, Norway, 2005.
[53] D. Xiang and A. Chen, “Fault-tolerant routing in 2D meshes/tori using limited -global-safety information,” Proc. of 31th? IEEE Int. Conf. on Parallel Processing, pp. 231-238,? Vancouver, Aug.,? 2002.
[54] 向东，张跃鲤，mesh网高效无死锁路由算法，《计算机学报》，vol. 30, no. 11, pp. 1954-1963, 2007.
[55] Z. Li , Y. Zhao, Y. Cui, and D. Xiang, “A density adaptive routing protocol for large-scale Ad hoc networks,” accepted to appear in Proc. of IEEE Wireless Communications and Networking Conference, 2008.
[56] D. Xiang, Y. Pan, Q. Wang, and Z. Chen, “Deadlock-free fully adaptive routing in 2-dimensional tori based on a new virtual network partitioning scheme,” accepted to appear in Proc. of 28th IEEE Int. Conference on Distributed Computing Systems, 2008.
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